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通过 I2C 兼容接口提供人机接口器件 (HID) 的低压 8x16 键盘扫描器这个 128 键位扫描器件专门针对操作系统为 Windows 8 的终端设备。 此器件与由已定义的 I2C 技术规范(1.0 版本)(由微软 (Microsoft) 定义)控制的 HID 完全兼容。 此 HID 和报告描述符被固化在器件程序代码中,这样就无需在生产时对它们进行编程。 此器件还有一个预先编程的键盘映射,此映射与大多数标准笔记本/台式机键盘兼容。 然而,也可以提供没有预先设定键盘的器件,这样在生产时可将任何键盘映射写入此器件。
具有中断逻辑和复位功能的 4 通道 I2C 和 SMBus 开关TCA9545A 是一款通过 I2C 总线控制的四路双向转换开关。 串行时钟/串行数据 (SCL/SDA) 上行对分散到四个下行对,或者通道。 根据可编程控制寄存器的内容,可选择任一单独 SCn/SDn 通道或者通道组合。 提供四个中断输入 (INT3-INT0),每个中断输入针对一个下行对。 一个中断 (INT) 输出可作为四个中断输入的与 (AND) 操作。
电平转换 FM+ I2C 总线中继器TCA9617A 是一款专门用于 I2C 总线和 SMBus 系统的 BiCMOS 双路双向缓冲器。 它能够在混合模式应用中提供低压(低至 0.8V)和更高压(2.2V 至 5.5V)之间的双向电压电平转换(上升转换和下降转换)。 电平转换期间,这个器件在不损失系统性能的情况下可扩展 I2C 和相似的总线系统。
BCD 到 7 段解码器/驱动器The '46A, '47A, and 'LS47 feature active-low outputs designed for driving, common-anode LEDs or incandescent indicators directly. The '48, 'LS48, and 'LS49 feature active-high outputs for driving lamp buffers or common-cathode LEDs. All of the circuits except 'LS49 have full ripple-blanking input/output controls and a lamp test input. The 'LS49 circuit incorporates a direct blanking input.
具有 10 个解码输出的 CMOS 十进制计数器CD4017B and CD4022B are 5-stage and 4-stage Johnson counters having 10 and 8 decoded outputs, respectively. Inputs include a CLOCK, a RESET, and a CLOCK INHIBIT signal. Schmitt trigger action in the CLOCK input circuit provides pulse shaping that allows unlimited clock input pulse rise and fall times.
具有施密特触发器输入的单路可再触发单稳多频振荡器The SN74LVC1G123 device is a single retriggerable monostable multivibrator designed for 1.65-V to 5.5-V VCC operation.
具有无错上电的 19 位 IEEE 1284 转换收发器The SN74LVCE161284 is designed for 3-V to 3.6-V VCC operation. This device provides asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.
具有三态输出的 19 位总线接口The SN74LVC161284 is designed for 3-V to 3.6-V VCC operation. This device provides asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.
19 位总线接口The SN74LV161284 is designed for 4.5-V to 5.5-V VCC operation. This device provides asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.
9 位至 18 位 HSTL-To-LVTTL 存储器地址锁存器This 9-bit to 18-bit D-type latch is designed for 3.15-V to 3.45-V VCC operation. The D inputs accept HSTL levels and the Q outputs provide LVTTL levels.
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